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The_Simulation_and_Research_of_SkyEye_Bascd_on_ARM
- ARM作为一种32位精简指令集CPU,其结构已经从 V3发展到V6,在嵌入式应用领域获得了巨大的成功,并在 小体积、低功耗、低成本、高性能的嵌入式应用领域确立了 市场领导地位。基于ARM构建的硬件仿真环境一SkyEye, 是~个可以运行嵌入式操作系统的硬件仿真工具,它可以 在没有硬件条件下进行嵌入式系统的学习和开发-ARM is a 32-bit RISC CPU, its structure has been developed to V3 from V6, the fie
MB87L2250_datasheet
- Datasheet for MB87L2250 - MPEG2 Transport, Video and Audio Decoder with integrated 32-Bit RISC CPU-Datasheet for MB87L2250- MPEG2 Transport, Video and Audio Decoder with integrated 32-Bit RISC CPU
RISC_CPU
- Verilog HDL编写的一个精简指令的处理器,很好用,可用来学习-Verilog HDL RISC_CPU
cpudesign
- Risc 32位CPU设计方法,由牛人主讲,可以好好学习-Risc 32 Wei CPU design methodology, from the cattle were speakers, you can learn
Chapter1-5
- 第一章到第五章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
S3C2440_H324
- 在现有的PSTN 网络上构建了一个嵌入式终端平台,该平台基于RISC 架构ARM 处理器S3C2440A,符合国际电联ITUT 建议的H.324 协议。此系统平台在原有的MCU+DSP 的架构基础上提出一种纯基于RISC 架构的ARM 处理器的可视电话 平台,该方案更加灵活, 可以用于现有的办公,家庭等环境.-Build a embedded platform of the ARM920T core RISC CPU S3C2440, which can connected to PST
RISC_CPU
- Verilog写的简单处理器QuartusII下可编译 //指令 操作码 源寄存器 目的寄存器 操作 // NOP 0000 xxxxx xxxxxx 空操作 //ADD 0001 src dest dest<=src+dest //SUB 0010 src dest dest<=dest-src //AND 0011 src dest dest<=src&&dest //NOT 0100 src dest dest<
PipelineCPU
- Quartus II 7.2环境中,采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
s1c33_uCos
- uCos在s1c33上的移植 S1C33 MCU EPSON最新的32位微处理器系列,专用于需要高级数据处理的便捷设备。 CPU性能 核心CPU 精工EPSON32位的RISC CPU,32位内部数据处理 33MHz 105条16位固定长度的指令 16个32位多用途的寄存器 在60MHZ操作下的最小指令执行时间为16.7ns 乘法、除法和MAC指令 内存 0~128K ROM 8K RAM 片内周边电路 晶振电路 32.769K~33MHz 定
cpudeliushuixianjiegou
- 根据流水线的基本原理 ,阐述了64位 RISC CPU的5级流水线结构和功能.重点介绍了流水线的 功能单元以及各单元的基本操作 流水线暂停和异常的处理方法 -According to the basic principles of line, 64-bit RISC CPU described the 5-stage pipeline structure and function. Focuses on the assembly line of functional units and th
RISC_CPU
- 利用VHDL实现risc cpu,IPcode 的risc cpu-Using VHDL implementation risc cpu, IPcode the risc cpu
VerilogHDLexample
- 可综合的VerilogHDL设计实例 ---简化的RISC CPU设计简介-VerilogHDL comprehensive design example can be simplified RISC CPU design--- Introduction---
NUC501_datasheet_A1.4
- 适合使用NUVOTON nuc501 做开发的参考。-The NUC501 is an ARM7TDMI-based MCU, specifically designed to offer low-cost and high-performance for various applications, like interactive toys, edutainment robots, and home appliances. It integrates the 32-bit RISC CPU w
sequencecontroller
- this is source code in verilog for sequence controller and clock generator which is used in RISC cpu
MSP430F149
- The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achi
risc8
- 基于verilog的8位risc-cpu源码,modelsim仿真-Verilog-based 8-bit risc-cpu source, modelsim simulation
risc
- 16位cpu的各功能模块的源程序,经过FPGA仿真通过,希望能帮到你-16-bit cpu' s each functional module of the source, through the FPGA emulation by, hope you can help
16F716[CH]
- 单片机内核特征: • 高性能RISC CPU • 只有35 条单字节指令 - 除了程序分支指令为双周期指令外,其它所有 指令均为单周期指令 • 工作速度:DC - 20 MHz 时钟输入 DC - 200 ns 指令周期 • 中断能力(多达7 个内部/ 外部中断源) • 8级深度硬件堆栈 • 直接、间接和相对寻址方式 特殊单片机特征: • 上电复位(POR) • 上电延
tiny64_latest.tar
- Descr iption Tiny64 A 64-Bit RISC CPU with minial resource usage. Every opcode is executed in 2 clock cycles. The word size is configurable via XLEN from 32 up to the FPGA limit. The assembler supports also differnet word sizes. Due simpli
cpu
- 实现了简单的精简指令集的CPU,里面带着原码-Create a Cpu of RISC